Demo entry 4072991

SHUBDIBABA

   

Submitted by anonymous on Mar 16, 2016 at 16:53
Language: vhdl. Code size: 1.9 kB.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity contador is
port( 
	clk, reset, echo : in std_logic; 
	bcd1 : out std_logic_vector (3 downto 0);
	bcd2 : out std_logic_vector (3 downto 0);
	bcd3 : out std_logic_vector (3 downto 0);
	bcd4 : out std_logic_vector (3 downto 0));
end contador;

architecture Behavioral of contador is
	signal bcd1_int : std_logic_vector (3 downto 0) := "0000";
	signal bcd2_int : std_logic_vector (3 downto 0) := "0000";
	signal bcd3_int : std_logic_vector (3 downto 0) := "0000";
	signal bcd4_int : std_logic_vector (3 downto 0) := "0000";
	signal cont : integer range 0 to 51 := 0;
begin

process (clk, reset) 
	begin -- process bcd_counting 
		if reset = '1' then -- asynchronous reset (active high)
			cont <= 0; 
			bcd1_int <= ( others => '0'); 
			bcd2_int <= ( others => '0'); 
			bcd3_int <= ( others => '0'); 
			bcd4_int <= ( others => '0'); 
		elsif clk'event and clk = '1' then -- rising clock edge 
		if (cont = 50) then 
			if echo = '1' then
				cont <= 1;
				if bcd1_int = "1001" then 
					bcd1_int <= "0000"; 
					if bcd2_int = "1001" then 
						bcd2_int <= "0000"; 
						if bcd3_int = "1001" then 
							bcd3_int <= "0000"; 
							if bcd4_int = "1001" then 
								bcd4_int <= "0000"; 
							else 
								bcd4_int <= bcd4_int + '1'; 
							end if; 
						else 
							bcd3_int <= bcd3_int + '1'; 
						end if; 
					else 
						bcd2_int <= bcd2_int + '1'; 
					end if; 
				else 
					bcd1_int <= bcd1_int + '1'; 
				end if;
			else 
			cont <= 0;
			end if;
		elsif echo = '1' then
			cont <= cont + 1;
		elsif echo = '0' then
			cont <= 0;
		end if;
end if;		 
		
end process; 

bcd1 <= bcd1_int;
bcd2 <= bcd2_int;
bcd3 <= bcd3_int;
bcd4 <= bcd4_int;

end Behavioral;

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