Demo entry 4073012

aergt

   

Submitted by anonymous on Mar 16, 2016 at 16:54
Language: vhdl. Code size: 1.8 kB.

-- VHDL do Fluxo de Dados

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Std_logic_arith.all;
use ieee.std_logic_unsigned.all;

ENTITY FD_sensor_de_distancia IS 
PORT (
      CLK			: IN   STD_LOGIC;
      ECHO			: IN   STD_LOGIC;
      RESET			: IN   STD_LOGIC;
	  MEDIDA		: OUT  STD_LOGIC_VECTOR(15 downto 0);
	  A7SEG3		: OUT  STD_LOGIC_VECTOR(6 downto 0);
	  A7SEG2			: OUT  STD_LOGIC_VECTOR(6 downto 0);
	  A7SEG1			: OUT  STD_LOGIC_VECTOR(6 downto 0);
	  A7SEG0			: OUT  STD_LOGIC_VECTOR(6 downto 0)
);
END ENTITY;

ARCHITECTURE arch_FD_sensor_de_distancia OF FD_sensor_de_distancia IS
SIGNAL sMEDIDA : STD_LOGIC_VECTOR(15 downto 0);
COMPONENT contador
PORT ( 
	clk, reset, echo : in std_logic; 
	bcd1 : out std_logic_vector (3 downto 0);
	bcd2 : out std_logic_vector (3 downto 0);
	bcd3 : out std_logic_vector (3 downto 0);
	bcd4 : out std_logic_vector (3 downto 0)
	);
END COMPONENT;

COMPONENT BCDto7segments
PORT (
		CLK 		: IN STD_LOGIC;
        BCD 		: IN STD_LOGIC_VECTOR(3 downto 0);  --BCD input
        segment7 	: OUT STD_LOGIC_VECTOR(6 downto 0)  -- 7 bit decoded output.
    );
END COMPONENT;
BEGIN

CONT : contador PORT MAP 	(CLK, RESET, ECHO, 
										sMEDIDA(3 downto 0),
										sMEDIDA(7 downto 4),
										sMEDIDA(11 downto 8),
										sMEDIDA(15 downto 12)
								);
MEDIDA <= sMEDIDA;								
SEG0: BCDto7segments PORT MAP (
								CLK,
								sMEDIDA(3 downto 0),
								A7SEG0
								);
SEG1: BCDto7segments PORT MAP (
								CLK,
								sMEDIDA(7 downto 4),
								A7SEG1
								);
SEG2: BCDto7segments PORT MAP (
								CLK,
								sMEDIDA(11 downto 8),
								A7SEG2
								);
SEG3: BCDto7segments PORT MAP (
								CLK,
								sMEDIDA(15 downto 12),
								A7SEG3
								);
END ARCHITECTURE;

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