Demo entry 4073037

fhdh

   

Submitted by anonymous on Mar 16, 2016 at 16:55
Language: vhdl. Code size: 1.4 kB.

-- VHDL do BCDto7segments

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Std_logic_arith.all;
use ieee.std_logic_unsigned.all;

ENTITY BCDto7segments IS
PORT (
		CLK 		: IN STD_LOGIC;
        BCD 		: IN STD_LOGIC_VECTOR(3 downto 0);  --BCD input
        segment7 	: OUT STD_LOGIC_VECTOR(6 downto 0)  -- 7 bit decoded output.
    );
END ENTITY;
--'a' corresponds to MSB of segment7 and g corresponds to LSB of segment7.
ARCHITECTURE arch_BCDto7segments of BCDto7segments IS
BEGIN
PROCESS (CLK, BCD)
BEGIN
	IF (clk'event and clk='1') THEN
		CASE BCD IS
			when "0000"=> segment7 <= "1000000"; -- "0000001";  -- '0'
			when "0001"=> segment7 <= "1111001"; -- "1001111";  -- '1'
			when "0010"=> segment7 <= "0100100"; -- "0010010";  -- '2'
			when "0011"=> segment7 <= "0110000"; --"0000110";  -- '3'
			when "0100"=> segment7 <= "0011001"; --"1001100";  -- '4' 
			when "0101"=> segment7 <= "0010010"; -- "0100100";  -- '5'
			when "0110"=> segment7 <= "0000010"; -- "0100000";  -- '6'
			when "0111"=> segment7 <= "1111000"; -- "0001111";  -- '7'
			when "1000"=> segment7 <= "0000000"; -- "0000000";  -- '8'
			when "1001"=> segment7 <= "0010000"; -- "0000100";  -- '9'
			--nothing is displayed when a number more than 9 is given as input. 
			when others=> segment7 <="1111111"; 
		END CASE;
	END IF;

END PROCESS;

END ARCHITECTURE;

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