Demo entry 6311198

VHDL

   

Submitted by anonymous on Oct 24, 2016 at 17:11
Language: vhdl. Code size: 4.7 kB.

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:23:25 10/15/2016 
-- Design Name: 
-- Module Name:    ALU - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ALU is
    Port ( clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           num : in  STD_LOGIC_VECTOR(0 to 15);
           Y : out  STD_LOGIC_VECTOR(15 downto 0));
			  
end ALU;

architecture Behavioral of ALU is
		--SIGNAL AA,BB,YY: std_logic_vector(15 downto 0) := "0000000000000000";
begin
	process(clk,rst) --状态改变
		variable AA,BB,YY: std_logic_vector(15 downto 0) := "0000000000000000";
		variable oper: std_logic_vector(3 downto 0) := "0000";
		variable cur_state: std_logic_vector(1 downto 0):= "00";
		--variable ff: std_logic_vector(15 downto 0) := "0000000000000000";
		variable tmp,O_F,S_F,C_F,Z_F,tmps: std_logic;
	begin
		if (rst = '0') then
			cur_state := "00";
		elsif (clk'event and clk = '1') then
			case cur_state is	--枚举状态
				when "00"=>
					AA := num;
					Y <= num;
					CUR_STATE := "01";
				when "01"=>
					BB := num;
					Y <= num;
					cur_state := "10";
				when "10"=>
					oper := num(12 to 15); 
					case oper is	--运算操作
						when "0000"=>
							YY := AA + BB;
						when "0001"=>
							YY := AA - BB;
						when "0010"=>
							YY := AA AND BB;
						when "0011"=>
							YY := AA OR BB;
						when "0100"=>
							YY := AA XOR BB;
						when "0101"=>
							YY := NOT AA;
						when "0110"=>
							YY := TO_STDLOGICVECTOR(TO_BITVECTOR(AA) SLL CONV_INTEGER(BB));
						when "0111"=>
							YY := TO_STDLOGICVECTOR(TO_BITVECTOR(AA) SRL CONV_INTEGER(BB));
						when "1000"=>
							YY := TO_STDLOGICVECTOR(TO_BITVECTOR(AA) SRA CONV_INTEGER(BB));
						when "1001"=>
							YY := TO_STDLOGICVECTOR(TO_BITVECTOR(AA) ROL CONV_INTEGER(BB));
						when others=>
							YY := "1111111111111111";
					end case;
					Y <= YY;
					cur_state := "11";
				when "11"=>
					--ff := "0000000011111111";
					--计算ff标志位!!
					--只需要判断加法减法的溢出即可
					if (oper = "0000") then
						tmp := (AA(15) and BB(15) and not YY(15)) or (not AA(15) and not BB(15) and YY(15)); 
						if (tmp = '1') then
							O_F := '1';
							Y(15) <= O_F;
							--Y <= "1111111111111111";
						else
							O_F := '0';
							Y(15) <= O_F;
							--Y <= "0000000000000000";
						end if;
						
						tmps := (AA(15) and BB(15)) or (AA(15) and not YY(15))or (BB(15) and not YY(15)); 
						if (tmps = '1') then
							C_F := '1';
							Y(13) <= C_F;
							--Y <= "1111111111111111";
						else
							C_F := '0';
							Y(13) <= C_F;
							--Y <= "0000000000000000";
						end if;
						
					elsif (oper = "0001") then
						tmp := (AA(15) and not BB(15) and not YY(15)) or (not AA(15) and BB(15) and YY(15)); 
						if (tmp = '1') then
							O_F := '1';
							Y(15) <= O_F;
						--Y <= "1111111111111111";
						else
							O_F := '0';
							Y(15) <= O_F;
							--Y <= "0000000000000000";
						end if;
						
						tmps := (AA(15) and not BB(15)) or (AA(15) and not YY(15))or ( not BB(15) and not YY(15)); 
						if (tmps = '1') then
							C_F := '1';
							Y(13) <= C_F;
							--Y <= "1111111111111111";
						else
							C_F := '0';
							Y(13) <= C_F;
							--Y <= "0000000000000000";
						end if;
						
					else
						O_F := '0';
						Y(15) <= O_F;
						C_F := '0';
						Y(13) <= C_F;
						--Y <= "0000000000000000";
					end if;
					
					if (YY = "0000000000000000") then
						Z_F := '1';
						Y(14) <= Z_F;
					else
						Z_F := '0';
						Y(14) <= Z_F;
						
						--Y <= "0000000000000000";
					end if;
					
					
					if (YY(15) = '1') then
						S_F := '1';
						Y(12) <= S_F;
					else
						S_F := '0';
						Y(12) <= S_F;
					end if;
					
					
					Y(11 downto 0) <="000000000000";
					--Y <= ff;
					cur_state := "00";
				WHEN OTHERS=>
			end case;
		end if;
	end process;
end Behavioral;

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