Demo entry 6327924

a simple verilog codes

   

Submitted by anonymous on Nov 25, 2016 at 08:47
Language: verilog. Code size: 230 Bytes.

module adder(
    input clk,
    input rst,
    input a,
    input b,
    output[1:0] q
);

reg[1:0] out;

always@(posedge clk)
begin
    if (rst)
       out <= 2'b00;
    else
       out <= a + b;
end

endmodule

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