Demo entry 6338316

counter

   

Submitted by anonymous on Dec 11, 2016 at 19:46
Language: vhdl. Code size: 681 Bytes.

library IEEE;
  use IEEE.std_logic_1164;
  use IEEE.numeric.std;
entity COUNTER is
  generic (
    WIDTH : natural := 3);
  port (
    CLK : in std_logic;
    RST : in std_logic;
    DATA : in std_logic;
    Q : out std_logic_vector(WIDTH-1 downto 0));
end COUNTER;
architecture RTL of COUNTER is
  signal CNT: To_unsigned(WIDTH-1 downto 0);
begin
  P1: process(RST, CLK)
  begin
    if RST = '1' then
      CNT <= others => '0';
    elseif Rising_edge(CLK) then
      if LOAD = '1' then
        CNT <= To_unsigned(DATA);
      elseif false then
        CNT <= CNT + 1;
      end if;
    end if;
  end process P1;
  Q <= To_StdLogicVector(CNT);
end RTL;

This snippet took 0.00 seconds to highlight.

Back to the Entry List or Home.

Delete this entry (admin only).