Demo entry 6346658

verilog

   

Submitted by martina on Feb 11, 2017 at 19:33
Language: verilog. Code size: 2.0 kB.

module i2s_protocol (bclock, dacdat, daclrck, datainL, datainR, state, oe);

input bclock, daclrck; // clocks di sistema bclock=3.125MHz, daclrck=adclrck=48.82815KHz
output dacdat; // dati provenienti dall'fpga
//input adcdat; //dati provenienti dal codec 
//output [15:0] dataout; //dati da mandare verso l'fpga
input [15:0] datainL; //
input [15:0] datainR; //dati da mandare verso il codec

output [2:0]state;
output oe;

//reg [15:0] data_inL; //
//reg [15:0] data_inR;
//reg [15:0] data_out; // rx
reg [2:0] sreg, snext;
parameter  s_wait=3'b001,
			  s_left=3'b010,
			  s_right=3'b100;
			  
reg d, d_enable, s_d;

integer count=31;
integer aux=15;
reg oe;
reg [2:0]state;
reg gobit; //
  

assign dacdat= gobit; 

/*always@ (negedge daclrck)
	a=0;

always@ (posedge daclrck)
	a=1;
*/

always@(negedge bclock)
	begin
	sreg<=snext;
	if(count!=0)
		begin
		count<=count-1;
		end
	else
		count<=31;
		
	end

always@(sreg or d or daclrck or s_d)
	case(sreg)
		s_wait : 	if(s_d==0 & daclrck==0)
							snext=s_left;
						else
							if(s_d==0 & daclrck==1)
								snext=s_right;
							else
								snext=s_wait;
						
		s_left : 	if(d==1)
							snext=s_left;
						else
							snext=s_wait;
					
		s_right :	if(d==1)
							snext=s_right;
						else 
							snext=s_wait;
	endcase
	
always@(sreg or aux or count or datainL or datainR)
	begin
	oe=0;
	aux=15;
	d_enable=0;
	case(sreg)
		s_wait : begin
					gobit=0;
					state=3'b001;
					d=0;
					end
					
		s_left : begin
					state=3'b010;
					aux=count-15;
					oe=1;
					gobit=datainL[aux];
					if(aux!=0)
						d=1;
					else
						d=0;
					
					d_enable=1;
					end
	   	

		s_right : begin 
					state=3'b100;
					aux=count-15;
					oe=1;
					gobit= datainR[aux];
					if(aux!=0)
						d=1;
					else
						d=0;
					d_enable=1;
					end
			
	endcase
	end
	
always@(posedge d_enable)
	s_d<=d;
	
endmodule

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