Demo entry 6351128

and

   

Submitted by anonymous on Mar 18, 2017 at 14:32
Language: vhdl. Code size: 201 Bytes.

entity myand is
    Port ( a : in STD_LOGIC;
           b : in STD_LOGIC;
           x : out STD_LOGIC);
end myand;

architecture Behavioral of myand is

begin

x<=a and b;

end Behavioral;

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