Demo entry 6351130

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Submitted by anonymous on Mar 18, 2017 at 14:43
Language: vhdl. Code size: 711 Bytes.

entity andor is
    Port ( u0 : in STD_LOGIC;
           u1 : in STD_LOGIC;
           u2 : in STD_LOGIC;
           u3 : in STD_LOGIC;
           output : out STD_LOGIC);
end andor;

architecture Behavioral of andor is

component myand
Port( a : in STD_LOGIC;
b : in STD_LOGIC;
x : out STD_LOGIC
);
end component;

component myor
Port( a : in STD_LOGIC;
b : in STD_LOGIC;
x : out STD_LOGIC
);
end component;

signal signal1 : std_logic:='0';
signal signal2 : std_logic:='0';

begin

and1 : myand port map(
a=>u0,
b=>u1,
x=>signal1
);

and2 : myand port map(
a=>u2,
b=>u3,
x=>signal2
);

or1 : myor port map(
a=>signal1,
b=>signal2,
x=>output
);

end Behavioral;

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