Demo entry 6351131

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Submitted by anonymous on Mar 18, 2017 at 14:47
Language: vhdl. Code size: 1.5 kB.

entity testbench is
--  Port ( );
end testbench;

architecture Behavioral of testbench is
component andor
Port( u0 : in STD_LOGIC;
u1 : in STD_LOGIC;
u2 : in STD_LOGIC;
u3 : in STD_LOGIC;
output : out STD_LOGIC
);
end component;
signal u0 : std_logic:='0';
signal u1 : std_logic:='0';
signal u2 : std_logic:='0';
signal u3 : std_logic:='0';
signal output : std_logic;
begin
uut : andor port map(
u0=>u0,
u1=>u1,
u2=>u2,
u3=>u3,
output=>output
);
process
begin
u0<='0';
u1<='0';
u2<='0';
u3<='0';
wait for 200 ns;
u0<='0';
u1<='0';
u2<='0';
u3<='1';
wait for 200 ns;
u0<='0';
u1<='0';
u2<='1';
u3<='0';
wait for 200 ns;
u0<='0';
u1<='0';
u2<='1';
u3<='1';
wait for 200 ns;

u0<='0';
u1<='1';
u2<='0';
u3<='0';
wait for 200 ns;
u0<='0';
u1<='1';
u2<='0';
u3<='1';
wait for 200 ns;
u0<='0';
u1<='1';
u2<='1';
u3<='0';
wait for 200 ns;
u0<='0';
u1<='1';
u2<='1';
u3<='1';
wait for 200 ns;

u0<='1';
u1<='0';
u2<='0';
u3<='0';
wait for 200 ns;
u0<='1';
u1<='0';
u2<='0';
u3<='1';
wait for 200 ns;
u0<='1';
u1<='0';
u2<='1';
u3<='0';
wait for 200 ns;
u0<='1';
u1<='0';
u2<='1';
u3<='1';
wait for 200 ns;

u0<='1';
u1<='1';
u2<='0';
u3<='0';
wait for 200 ns;
u0<='1';
u1<='1';
u2<='0';
u3<='1';
wait for 200 ns;
u0<='1';
u1<='1';
u2<='1';
u3<='0';
wait for 200 ns;
u0<='1';
u1<='1';
u2<='1';
u3<='1';
wait for 200 ns;


end process;
end Behavioral;

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