Demo entry 6351132

l

   

Submitted by anonymous on Mar 18, 2017 at 14:51
Language: vhdl. Code size: 1.3 kB.

entity mem is
    Port ( input : in STD_LOGIC_VECTOR (3 downto 0);
           output : out STD_LOGIC_VECTOR (7 downto 0));
end mem;

architecture Behavioral of mem is

begin
 process (input)
    begin
        if input="0000" then
            output<="00000000";
        elsif input="0001" then
            output<="00000001";
        elsif input="0010" then
            output<="00000011";
        elsif input="0011" then
            output<="00000111";
        elsif input="0100" then
            output<="00001111";
        elsif input="0101" then
            output<="00011111";
        elsif input="0110" then
            output<="00111111";
        elsif input="0111" then
            output<="01111111";
        elsif input="1000" then
            output<="11111111";
        elsif input="1001" then
            output<="11111110";
        elsif input="1010" then
            output<="11111100";
        elsif input="1011" then
            output<="11111000";
        elsif input="1100" then
            output<="11110000";
        elsif input="1101" then
            output<="11100000";
        elsif input="1110" then
            output<="11000000";
        elsif input="1111" then
            output<="10000000";      
        end if;
    end process ;
end Behavioral;

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