Demo entry 6351133

k

   

Submitted by anonymous on Mar 18, 2017 at 14:53
Language: vhdl. Code size: 1.2 kB.

entity test is
--  Port ( );
end test;

architecture Behavioral of test is
component mem
Port( input : in STD_LOGIC_vector(3 downto 0);
output : out STD_LOGIC_vector(7downto 0)
);
end component;
signal input:std_logic_vector(3 downto 0):="0000";
signal output:std_logic_vector(7 downto 0);
begin
    uut : mem port map(
        input=>input,
        output=>output
        );
    process
    begin
        input<="0000";
        wait for 1ns;
        input<="0001";
        wait for 1ns;
        input<="0010";
        wait for 1ns;
        input<="0011";
        wait for 1ns;
        input<="0100";
        wait for 1ns;
        input<="0101";
        wait for 1ns;
        input<="0110";
        wait for 1ns;
        input<="0111";
        wait for 1ns;
        input<="1000";
        wait for 1ns;
        input<="1001";
        wait for 1ns;
        input<="1010";
        wait for 1ns;
        input<="1011";
        wait for 1ns;
        input<="1100";
        wait for 1ns;
        input<="1101";
        wait for 1ns;
        input<="1110";
        wait for 1ns;
        input<="1111";
        wait for 1ns;
    end process;
end Behavioral;

This snippet took 0.00 seconds to highlight.

Back to the Entry List or Home.

Delete this entry (admin only).