Demo entry 6351134

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Submitted by anonymous on Mar 18, 2017 at 14:55
Language: vhdl. Code size: 589 Bytes.

entity clk_div is
    Port ( input : in STD_LOGIC;
           output : out STD_LOGIC);
end clk_div;

architecture Behavioral of clk_div is

begin
    process(input) 
        variable count:integer :=0; 
        variable inv:STD_LOGIC:='0';
    begin
        if (input'event =true and input='1') then
            count:=count+1;
            if count=100000000 then  
                inv:=not inv;
                output<=inv;
                count:=0;
            end if;
        else 
            output<=inv;    
        end if;  
    end process;
end Behavioral;

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