Demo entry 6351135

d

   

Submitted by anonymous on Mar 18, 2017 at 14:56
Language: vhdl. Code size: 470 Bytes.

entity test is
--  Port ( );
end test;

architecture Behavioral of test is
component clk_div
Port( input : in STD_LOGIC;
output : out STD_LOGIC
);
end component;
signal input:std_logic:='0';
signal output:std_logic;
begin
    uut : clk_div port map(
        input=>input,
        output=>output
        );
    process
    begin
        input<='0';
        wait for 5ns;
        input<='1';
        wait for 5ns;
    end process;

end Behavioral;

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