Demo entry 6351136

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Submitted by anonymous on Mar 18, 2017 at 14:58
Language: vhdl. Code size: 862 Bytes.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_signed.ALL;

entity addr is
    Port ( ce : in STD_LOGIC;
           clk : in STD_LOGIC;
           res : in STD_LOGIC;
           output : out STD_LOGIC_VECTOR (3 downto 0));
end addr;

architecture Behavioral of addr is
begin
    process(res,ce)
    variable count:STD_LOGIC_VECTOR (3 downto 0):="0000";
    begin
        if res='1' then
            count:="0000";
            output<=count;
        else
            if (ce'event =true and ce='1') then
                
                if count="1111" then
                    count:="0000";
                    output<=count;
                else
                    count:=count+"0001";
                    output<=count;
                end if;
            end if;
        end if;
    end process;
end Behavioral;

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