Demo entry 6351137

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Submitted by anonymous on Mar 18, 2017 at 15:00
Language: vhdl. Code size: 622 Bytes.

entity test is
--  Port ( );
end test;

architecture Behavioral of test is

component addr
Port( ce : in STD_LOGIC;
clk : in STD_LOGIC;
res : in STD_LOGIC;
output : out STD_LOGIC_vector(3 downto 0));
end component;

signal ce:std_logic:='0';
signal clk:std_logic:='0';
signal res:std_logic:='0';
signal output:std_logic_vector(3 downto 0);

begin
    uut : addr port map(
        ce=>ce,
        clk=>clk,
        res=>res,
        output=>output
        );
    process
    begin
        ce<='0';
        wait for 5ns;
        ce<='1';
        wait for 5ns;
    end process;
end Behavioral;

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