Demo entry 6351138

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Submitted by anonymous on Mar 18, 2017 at 15:02
Language: vhdl. Code size: 1.4 kB.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity cntr is
    generic(n:integer:=4);
    Port ( data : in STD_LOGIC_vector(n-1 downto 0);
           ce : in STD_LOGIC;
           load : in STD_LOGIC;
           updn : in STD_LOGIC;
           clk : in STD_LOGIC;
           res : in STD_LOGIC;
           q : out STD_LOGIC_vector(n-1 downto 0)
          );
end cntr;

architecture Behavioral of cntr is

shared variable count:STD_LOGIC_VECTOR (n-1 downto 0):=(others=>'0');
shared variable a:STD_LOGIC_VECTOR (n-1 downto 0):=(others=>'1');

begin

process(data,ce,load,updn,clk,res) 
begin
 if res='1' then
    count:=(others=>'0');
    q<=(others=>'0');
else
    if load='1' then
       q<=data;
    else
        if ce='1' then
            if (clk'event =true and clk='1') then
                if updn='1' then
                    if count=a then
                        q<=count;
                        count:=(others=>'0');
                        
                    else
                        q<=count;
                        count:=count+1;
                    end if;
                else
                    if count/=0 then
                        count:=count-1;
                    end if;
                    q<=count;
                end if;
            end if;
        end if;
    end if;
end if;
end process;

end Behavioral;

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