Demo entry 6351139

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Submitted by anonymous on Mar 18, 2017 at 15:03
Language: vhdl. Code size: 1.2 kB.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity test is
--  Port ( );
generic(n:integer:=4);
end test;

architecture Behavioral of test is

component cntr

Port ( data : in STD_LOGIC_vector(n-1 downto 0);
       ce : in STD_LOGIC;
       load : in STD_LOGIC;
       updn : in STD_LOGIC;
       clk : in STD_LOGIC;
       res : in STD_LOGIC;
       q : out STD_LOGIC_vector(n-1 downto 0)
     );
end component;

signal data:std_logic_vector(n-1 downto 0):=(others=>'1');
signal ce:std_logic:='1';
signal load:std_logic:='0';
signal updn:std_logic:='1';
signal clk:std_logic:='0';
signal res:std_logic:='0';
signal q:std_logic_vector(n-1 downto 0);

begin
    uut : cntr port map(
        data=>data,
        ce=>ce,
        load=>load,
        updn=>updn,
        clk=>clk,
        res=>res,
        q=>q
        );
    process
    begin
    
        clk<='0';
        wait for 5ns;
        clk<='1';
        wait for 5ns;
        
        clk<='0';

  --      res<='1';
        wait for 5ns;
    --    res<='0';

        clk<='1';
        wait for 5ns;
    end process;

end Behavioral;

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