Demo entry 6354110

FSM

   

Submitted by anonymous on Apr 05, 2017 at 11:37
Language: verilog. Code size: 6.3 kB.

module vend(clk,rst,led,clarm,dis_price,N,KEYI1,KEYI2,KEYI3,KEYI4,com1);
  input clk;
  input rst;
  input KEYI1,KEYI2,KEYI3,KEYI4;
  output [7:0] led;
  output com1;
  output clarm;
  output [6:0] dis_price;
  output [6:0]  N;
  
  wire clk_1;
  reg [2:0] mon;
  reg [3:0]light;
  reg times;
  reg clk_2hz;
  reg [7:0] led;
  reg clarm;
  reg [6:0] dis_price;
  reg [6:0] N;
  reg [31:0] cnt;
  reg [2:0]  state;
  wire  coin;
  reg [3:0] number;
  reg [27:0] counter;

  wire            clk_64Hz;
  wire  KEYO1,KEYO2,KEYO3,KEYO4;

 
  parameter SET_TIME_20MS = 20'd1_000_000;
  parameter S1 = 3'b000, S2 = 3'b001, S3 = 3'b010, S4 = 3'b011, S5 = 3'b100, S6 = 3'b101;
  parameter Num1 = 4'b0001, Num2 = 4'b0010, Num3 = 4'b0011, Num4 = 4'b0100, Num5 = 4'b0101, Num6 = 4'b0110, 
            Num7 = 4'b0111, Num8 = 4'b1000, Num9 = 4'b1001, Num0 = 4'b0000;
  assign com1 = 0;
  assign com2 = 0;
  
  defreq_50MHz(.clk_50MHz(clk), .clk_1Hz(clk_64Hz));
  Pocess_KEY(.out_key1(KEYO1),.out_key2(KEYO2),.out_key3(KEYO3),.out_key4(KEYO4),.clock_64Hz(clk_64Hz)
                  ,.key1(KEYI1),.key2(KEYI2),.key3(KEYI3),.key4(KEYI4));


	
 always@(posedge clk_64Hz )
  begin
  
    if(!rst)
	  
	     begin
           led <= 0;
			  clarm <= 1'b0;
			  state <= S1;
		  end
	  else  
		     case(state)
			  S1:
			  begin
			         if(KEYO4)
			         begin			
						state <= S2;
						end
  
						else
						begin
						  state <= S1;
						  dis_price <= 7'b1000000;
						  led <= 0;
						  
						  if(KEYO3 == 1)
						    begin
						    clarm = 1; 
						    end
						  else
						    begin
						    clarm = 0;
						    end
						end
						
			  end
			  S2:		
			  begin
                  if(KEYO4)
						
			         begin
						state <= S3;
						end

						else
				      begin
						  dis_price <= 7'b1111001;
				        state <= S2;
						  led[0] <= 1;
						  if(KEYO3 == 1)
						    begin
						    clarm = 1; 
							 end
						  else
						    begin
						    if(KEYO2 == 1)
							 clarm = 1;
							 else
							 clarm = 0;
							 end 
						end
						
			  end
			  S3:		
			  begin
			  
			         if(KEYO4)
						
			         begin
						state <= S4;
						end

						else
						begin
						  dis_price <= 7'b0100100;
						  state <= S3;
						  led[1] <= 1;
						  if(KEYO3 == 1)
						     begin
							  clarm = 1;
							  end
						  else
						     clarm = 0; 
						end
			  end
			  S4:		
			  begin
			  
			         if(KEYO4)
						
			         begin
						state <= S5;
						end

						else
						begin
						  dis_price <= 7'b0110000;
						  state <= S4;
						  led[2] <= 1;
						  if(KEYO3 == 1)
						     begin
							  clarm = 1;
							  end
						  else
						     clarm = 0; 
						end
			  end
			  S5:		
			  begin
			         if(KEYO4)
						
			         begin
						state <= S6;
						end
           
						else
						begin
						  dis_price <= 7'b0011001;
						  state <= S5;
						  led[3] <= 1;
						  if(KEYO3 == 1)
						     begin
						     clarm = 1;
							  end
						  else
						  begin
						     clarm = 0; 
						  end
						
						end
			  end
			  S6:			
    	  	  begin
			         if(KEYO4)
						
			         begin
						state <= S2;
						led<=0;
						end

						else
						begin 
						dis_price <= 7'b0010010;
						state <= S6;
						led[4] <= 1;
						  if(KEYO3 == 1)
						     begin
						     clarm = 0;
							  state <= S1;
							  if(counter == 8'd64)
							    begin
							      led <= ~led;
								   counter <= 8'd00;
								end
							  end
						  else
						     begin
						     clarm = 0; 
						     end
						end
			  end


			 endcase
			 
 end
endmodule
/*
always@(posedge clk_64Hz)
if(!rst)
   number <= Num0;
else
 begin	
 if (state == S6 )
  begin
  number <= number + 1;
  case(number)
  Num0:begin dis_price <= 7'b1000000;  end
  Num1:begin dis_price <= 7'b1111001;  end
  Num2:begin dis_price <= 7'b0100100;  end
  Num3:begin dis_price <= 7'b0110000;  end
  Num4:begin dis_price <= 7'b0110000;  end
  Num5:begin dis_price <= 7'b0010010;  end
  Num6:begin dis_price <= 7'b0000010;  end
  Num7:begin dis_price <= 7'b1111000;  end
  Num8:begin dis_price <= 7'b0000000;  end
  Num9:begin dis_price <= 7'b0010000;  end
  Num9:begin dis_price <= 7'b1000000;  end
  
  endcase
  end
  end
 */



module Pocess_KEY(out_key1,out_key2,out_key3,out_key4,clock_64Hz,key1,key2,key3,key4);
     input clock_64Hz,key1,key2,key3,key4;
	  output reg out_key1,out_key2,out_key3,out_key4;
	
     reg [3:0]q,x;
	  
	  always@(posedge clock_64Hz)
	  begin
	     q<={key4,~key3,~key2,key1};
		
	  end
	  
		always@(negedge q[3] or negedge clock_64Hz ) 
	       if(q[3]==1'b0)
			   begin
				 out_key4<=1'b0;
				 x[3]<=1'b0;
				  
			   end
			 else if (x[3]==1'b0)
			      if (out_key4==1'b0)
					   out_key4<=1'b1;
			 else if (out_key4<=1'b1)
			   begin
				   out_key4<=1'b0;
					x[3]<=1'b1;
				end
				
		always@(posedge q[2] or posedge clock_64Hz ) 
	       if(q[2]==1'b1)
			   begin
				 out_key3<=1'b0;
				 x[2]<=1'b1;
				  
			   end
			 else if (x[2]==1'b1)
			      if (out_key3==1'b0)
					   out_key3<=1'b1;
			 else if (out_key3==1'b1)
			   begin
				   out_key3<=1'b0;
					x[2]<=1'b0;
				end
				
		always@(posedge q[1] or negedge clock_64Hz ) 
	       if(q[1]==1'b1)
			   begin
				 out_key2<=1'b0;
				 x[1]<=1'b1;
				  
			   end
			 else if (x[1]==1'b1)
			      if (out_key2==1'b0)
					   out_key2<=1'b1;
			 else if (out_key2==1'b1)
			   begin
				   out_key2<=1'b0;
					x[1]<=1'b1;
				end
				
		always@(posedge q[0])
		
		   out_key1<=~out_key1;
		
endmodule
			    
					



module defreq_50MHz (input clk_50MHz, output clk_1Hz);

reg [18:0] q1;
reg [6:0]  q0;

     always@(posedge clk_50MHz)
		 
		   begin	
			    if(q1==19'h5F5E0) 
				    q1 <= 19'h00000;
			    else
				    q1 <= q1 + 1;		
	      end
			
	  always@(negedge q1[18])
	  
	       q0<= q0 + 1;
			 
		    assign clk_1Hz = q0[1];
			 
endmodule
	

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