Demo entry 6354483

Verilog Generator

   

Submitted by Le Minh Son on Apr 07, 2017 at 05:58
Language: Python 3. Code size: 2.8 kB.

from __future__ import absolute_import
from __future__ import print_function
import sys
import os
import collections

from veriloggen import *

def mkexample():
    name_of_file = input("Enter the name of file: ")
    filename = os.path.dirname(os.path.abspath(__file__)) + '/' + str(name_of_file) + '.v'
    modules = from_verilog.read_verilog_module(filename)
    m = modules['example']   
    return m

def mkTop():
    m = Module('example_top')
    #width = m.Parameter('DATA_WIDTH', 8)
    #example_a_in = m.Wire('example_a_in')
    #example_b_in = m.Wire('example_b_in',width)
    #example_c_inout = m.Wire('example_c_inout')
    #example_d_out = m.Wire('example_d_out')

    example = mkexample()
    ex_ports = example.get_ports()

    # Get keys (uaually name) in OrderedDict
    ex_ports_list_key_ordereddict = ex_ports.keys()

    # Get values in OrderedDict
    #ex_ports_list_value_ordereddict = ex_ports.values()
 
    # Find length of ex_ports_list_key_length
    ex_ports_list_key_length = len(ex_ports_list_key_ordereddict)

    # Initiate example ports list & ports instance list
    ex_ports_list = []
    ports_instance = []
    for key in ex_ports_list_key_ordereddict:
        ex_ports_list.append(key)
        
    # Create Ports of module Top
    for i in range(0, ex_ports_list_key_length):
        ports = ex_ports[ex_ports_list[i]]
        if ports.width_msb is None:
            example_top_ports_name = str(example.name) + "_" + str(ports)
            example_top_ports = m.Wire(example_top_ports_name)
            ports_instance.append(example_top_ports)

        elif str(ports.width_msb).isdigit()==True and int(str(ports.width_msb)) != 0:
            width = int(str(ports.width_msb)) + 1
            example_top_ports_name = str(example.name) + "_" + str(ports)
            example_top_ports = m.Wire(example_top_ports_name, width)
            ports_instance.append(example_top_ports)
       
        else:
            a = str(ports.width_msb)
            b = "1-() "
            for char in b:
                a = a.replace(char,"")
            #width = m.Parameter('DATA_WIDTH', 8)
            width = m.copy_params(example)
            width = width[a]
            #print (width)
            example_top_ports_name = str(example.name) + "_" + str(ports)
            example_top_ports = m.Wire(example_top_ports_name,width)
            ports_instance.append(example_top_ports)

    # Copy Parameters and Ports in order to create Module Instantiaton
    params = m.copy_params(example)
    #print (ports_instance)

    # Make Instance
    m.Instance(example, 'example_0', params, ports_instance)

    return m

if __name__ == '__main__':
    top = mkTop()
    # Create module_top file from AST Tree
    verilog = top.to_verilog(filename='module_top.v')
    print(verilog)

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