Demo entry 6356026

verilog HDL

   

Submitted by KK on Apr 16, 2017 at 09:39
Language: verilog. Code size: 1.1 kB.

// Removal of key jitter module
module button(input CLK_50M,clk,key, output reg coin);
reg k;
reg buff;
reg [19:0]delay;

//less than 20ms is invalued 
always@(posedge CLK_50M)
begin
 if(key==1'b0 && delay<= 20'd1000000)   //count to 20ms
     begin
         k<=0;
	 delay<=delay+1'b1;
     end
else if (key==1'b0 && delay > 20'd1000000)//more than 20ms and key is still pressed
       k<=1;
else
    begin
       k<=0;         //other condition is 0
       delay<=0;
    end
end

  
always@(negedge clk)   //negedge valued only 1 cycle 
begin
     if( key==1'b0 && k==1 )   //the first negedge give all to 0 and wait
        begin	
	  coin<=0;
          buff<=0;               
        end
else if(buff==0&& coin ==0)	  
      coin<=1;           //the second negedge and key is 0 give output 1 and wait
else if(coin==1)
      begin                //the third negedge state has  changed and give output 0 buffer 1 
       coin<=0;
       buff<=1;
       end
else 
  coin<=0;        //other condition is invalued
end

endmodule
    

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