Demo entry 6356720

dd

   

Submitted by a on Apr 20, 2017 at 09:41
Language: verilog. Code size: 586 Bytes.

module bucket_sft32(datain,dataout,d,s,shift);
 input [31:0]datain;
 output reg [31:0]dataout;
 input d,s;                       //左移(0)右移(1)控制信号,循环(0)逻辑(1)移位选择信号
 input [4:0]shift;              //移位位数控制信号
 
 always@(datain)
  case({d,s})
   2'b00: 
    begin
     dataout=shift[4]?{datain[15:0],datain[31:16]}:datain;
     dataout=shift[3]?{dataout[23:0],dataout[31:24]}:dataout;
     dataout=shift[2]?{dataout[27:0],dataout[31:28]}:dataout;
     dataout=shift[1]?{dataout[29:0],dataout[31:30]}:dataout;
     dataout=shift[0]?{dataout[30:0],dataout[31]}:dataout;
    end

This snippet took 0.00 seconds to highlight.

Back to the Entry List or Home.

Delete this entry (admin only).