Demo entry 6357630

c

   

Submitted by anonymous on Apr 23, 2017 at 14:32
Language: vhdl. Code size: 1.5 kB.

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 2017/04/13 18:47:17
-- Design Name: 
-- Module Name: clk_div - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity clk_div is
    Port ( clk : in STD_LOGIC;
           output : out STD_LOGIC);
end clk_div;

architecture Behavioral of clk_div is
signal count:integer :=0; 
signal inv:STD_LOGIC:='0';
begin
    process(clk) 
--        variable count:integer :=0; 
--       variable inv:STD_LOGIC:='0';
    begin
        if rising_edge(clk)then   
            if count=10 then  
                inv<=not inv;
                output<=clk;
                count<=0;
            else
                count<=count+1;
                output<=inv;
            end if;
    
        end if;  
    end process;
end Behavioral;

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