Demo entry 6359929

s

   

Submitted by anonymous on Apr 30, 2017 at 15:15
Language: verilog. Code size: 166 Bytes.

module compare_eight(q,a,b);
    input [7:0]a;
    input [7:0]b;
    output q;
    reg q;
    always  @(a or  b)
    if(a>b)
      q=1;
    else
      q=0;
endmodule

This snippet took 0.00 seconds to highlight.

Back to the Entry List or Home.

Delete this entry (admin only).