Demo entry 6360345

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Submitted by anonymous on May 01, 2017 at 12:03
Language: verilog. Code size: 1.5 kB.

module  stair_light(light,switch,rst,clk10,state);
  input clk10,rst;
  input[2:0]switch;
  output[2:0]light;
  output[2:0]state;
  reg[2:0]state;
  reg[7:0]i1,i2,i3,t11,t12,t21,t22,t31,t32;
  reg e1,e2,e3,e1_d,e2_d,e3_d;
  wire [3:0]light;
  wire [3:0]switch;
  
  assign  light[2]=state[2];
  assign  light[1]=state[1];
  assign  light[0]=state[0];
  
  //light
  always@(posedge clk10)
    begin
      if(switch[2])
        begin
          i1=i1+1;
          if(i1<=5)
            e1=0;
          else
            begin
              e1=1;
              t11=80-i1;
              t12=40;
            end
         end
         
      else
        begin 
          if(i1<=80)
            begin
              t11=t11-1;
              if(t11==0)
                begin
                  e1=0;
                  i1=0;
                end
            end
          if(i1>80)
            begin
              t12=t12-1;
              if(t12==0)
                begin
                  e1=0;
                  i1=0;
                end
            end
        end
    end
              t21=80-i2;
              t22=40;
            end
         end
         
      else
        begin 
          if(i2<=80)
            begin
              t21=t21-1;
              if(t21==0)
                begin
                  e2=0;
                  i2=0;
                end
            end
          if(i2>80)

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