Demo entry 6360395

tt

   

Submitted by tt on May 01, 2017 at 15:01
Language: verilog. Code size: 1.2 kB.

`timescale 1ns / 1ps

module fifo(
   input         clk,
   input         rst,
   input         wr,
   input         rd,
   input  [7:0] din,
   output [7:0] dout,
   output        empty,
   output        full,
   output  [4:0] dcnt
)/* synthesis syn_hier = "hard" */;

// Generating 16-deep SRL based shift register (no reset)
integer i;
reg [7:0] srl_shr[15:0];
always @ (posedge clk)
if (wr) begin
   for (i=15; i>0; i=i-1) begin
      srl_shr[i] <= srl_shr[i-1];
   end
   srl_shr[0] <= din;
end

// Data counter with the ability to count from 0 to 16
reg [4:0] srl_dcnt;
always @ (posedge clk)
if (rst)
   srl_dcnt <= 0;
else
   if (wr & ~rd)
      srl_dcnt <= srl_dcnt + 1;
   else if (~wr & rd)
      srl_dcnt <= srl_dcnt - 1;

assign dcnt = srl_dcnt;

// Read address for the SRL, 5 bit wide
reg [4:0] srl_addr;
always @ (posedge clk)
if (rst)
   srl_addr <= 5'h1F;
else
   if (wr & ~rd)
      srl_addr <= srl_addr + 1;
   else if (~wr & rd)
      srl_addr <= srl_addr - 1;

// FIFO status signals
assign empty = srl_addr[4];
assign full  = srl_dcnt[4];      

// Asyncronous data output
assign dout =srl_shr[srl_addr[3:0]];


endmodule

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