Demo entry 6637161

1

   

Submitted by anonymous on Aug 30, 2017 at 12:39
Language: verilog. Code size: 592 Bytes.

if (dmareq&&(!busy))
case(dmareq)
4'b0001:
	begin
		write_m<=1'b0;
		addr_m<=src_addr0;
		size_m<=src_width0;
		if (src_len0<src_bsize0)
			begin
				src_cnt<=src_len0;
				burst_m<=3'b001;
				incr_num<=src_len0 - 1;  //Match with AHB Master Interface
			end
		else if (src_bsize0<=src_len0)
			begin
				src_cnt<=src_bsize0;
				case(src_bsize0)
				`SINGLE: burst_m<=3'b000;
				`INCR4: burst_m<=3'b011;
				`INCR8: burst_m<=3'b101;
				`INCR16: burst_m<=3'b111;
				default: burst_m<=3'b111;
				endcase
			end
	end
4'b0010:
4'b0100:
4'b1000:
default:
endcase

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