Demo entry 6647718

123

   

Submitted by 1234 on Oct 21, 2017 at 09:30
Language: verilog. Code size: 8.7 kB.

module example(input  a, b, c,
               output y);//输入a,b,c,输出y
  assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b &  c;y赋值,ya,b,c的一个逻辑函数
endmodule


module and3(input  a, b, c,
            output y);//三输入与门
  assign y = a & b & c; //赋值
endmodule

module inv(input  a,
           output y);//非门
  assign y = ~a;//赋值
endmodule

module nand3(input  a, b, c
             output y);
  logic n1;                   // internal signal//定义n1
  and3 andgate(a, b, c, n1);  // instance of and3//模块例化
  inv  inverter(n1, y);       // instance of inv//模块例化
endmodule

module gates(input  [3:0] a, b,
             output [3:0] y1, y2, y3, y4, y5);
   /* Five different two-input logic 
      gates acting on 4 bit busses */
   assign y1 = a & b;    // AND//赋值,与
   assign y2 = a | b;    // OR //赋值,或
   assign y3 = a ^ b;    // XOR //赋值,异或
   assign y4 = ~(a & b); // NAND //赋值,与非
   assign y5 = ~(a | b); // NOR //赋值,或非
endmodule

module and8(input [7:0] a, 
            output y);
   assign y = &a;//y为a的逐位与
   // &a is much easier to write than
   // assign y = a[7] & a[6] & a[5] & a[4] &
   //            a[3] & a[2] & a[1] & a[0];
endmodule

module mux2(input [3:0] d0, d1, 
            input  s,
            output [3:0] y);//二路选择器
   assign y = s ? d1 : d0;//s是1,y是d1,s是0,y是d0 
endmodule

module fulladder(input  a, b, cin, 
                 output s, cout);//一位全加器
  logic p, g;   // internal nodes//定义中间变量
  assign p = a ^ b;//赋值,异或
  assign g = a & b;//赋值,与
  
  assign s = p ^ cin;//赋值,异或
  assign cout = g | (p & cin);//赋值
endmodule

assign y = {a[2:1], {3{b[0]}}, a[0], 6b100_010}//位拼接

module mux2_8(input [7:0] d0, d1,
              input  s,
              output [7:0] y);
  mux2 lsbmux(d0[3:0], d1[3:0], s, y[3:0]);//
  mux2 msbmux(d0[7:4], d1[7:4], s, y[7:4]);//例化模块,拼接为y
endmodule

module tristate(input [3:0] a, 
                input  en, 
                output [3:0] y);
   assign y = en ? a : 4bz;//控制器,a带有使能
endmodule

module flop(input  clk, 
           input  [3:0] d, 
           output [3:0] q);//D触发器
  always@(posedge clk)//always是赋值关键字,posedge clk表示在时钟上升沿进行赋值
    q <= d; // pronounced “q gets d”//<=非阻塞式赋值
endmodule

module flopr(input  clk,
             input  reset, 
             input [3:0] d, 
             output [3:0] q);//可复位的D触发器
 
  // synchronous reset
  always@(posedge clk)
    if (reset) q <= 4b0;//选择语句
    else       q <= d;
endmodule

module flopr(input  clk,
             input  reset, 
             input [3:0] d, 
             output [3:0] q);//异步复位模块
   
  // asynchronous reset
  always @(posedge clk, posedge reset)//异步复位
    if (reset) q <= 4'b0;
    else       q <= d;
endmodule

module flopr(input  clk,
             input  reset, 
             input [3:0] d, 
             output [3:0] q);//可复位的D触发器
 
  // synchronous reset
  always@(posedge clk)//同步复位
    if (reset) q <= 4b0;//选择语句
    else       q <= d;
endmodule

module flopr(input  clk,
             input  reset, 
             input [3:0] d, 
             output [3:0] q);//异步复位模块
   
  // asynchronous reset
  always @(posedge clk, posedge reset)//异步复位
    if (reset) q <= 4'b0;
    else       q <= d;
endmodule

module flopren(input  clk,
               input  reset, 
               input  en, 
               input [3:0] d, 
               output [3:0] q);//带有使能的异步复位电路
  // asynchronous reset and enable 
  always@(posedge clk, posedge reset)//在clk或reset上升沿赋值
    if      (reset) q <= 4'b0;
    else if (en)    q <= d;
endmodule 

module latch(input            clk, 
             input      [3:0] d, 
             output reg [3:0] q);//锁存器
  always@(*)//状态有变,赋值
    if (clk) q <= d;
endmodule

// combinational logic using an always statement
module gates(input      [3:0] a, b, 
             output reg [3:0] y1, y2, y3, y4, y5);
  always@(*)       // need begin/end because there is//组合逻辑电路中使用always,
    begin            // more than one statement in always//多条语句使用begin,end
      y1 = a & b;    // AND
      y2 = a | b;    // OR
      y3 = a ^ b;    // XOR
      y4 = ~(a & b); // NAND
      y5 = ~(a | b); // NOR
    end
endmodule

module sevenseg(input      [3:0] data, 
                output reg [6:0] segments);//七段显示译码器
  always@(*)
    case (data)        //case语句(无优先级),需考虑所有情况
      //                     abc_defg     
      0: segments =       7'b111_1110;
      1: segments =       7'b011_0000;
      2: segments =       7'b110_1101;
      3: segments =       7'b111_1001;
      4: segments =       7'b011_0011;
      5: segments =       7'b101_1011;
      6: segments =       7'b101_1111;
      7: segments =       7'b111_0000;
      8: segments =       7'b111_1111;
      9: segments =       7'b111_0011;
      default: segments = 7b000_0000; // required//default,默认情况
    endcase
endmodule  

module priority_casez(input      [3:0] a, 
                      output reg [3:0] y);//优先编码器
  always@(*)
    casez(a)
      4'b1???: y = 4'b1000;  // ? = don’t care
      4b01??: y = 4b0100;//?表示不在乎是0或1
      4'b001?: y = 4'b0010;
      4'b0001: y = 4'b0001;
      default: y = 4'b0000;
   endcase
endmodule   

// Good synchronizer using 
// nonblocking assignments
module syncgood(input      clk,
                input      d,
                output reg q);
  reg n1;
  always@(posedge clk)
    begin
      n1 <= d;  // nonblocking
      q  <= n1; // nonblocking
    end                      //非阻塞式赋值
endmodule

// Bad synchronizer using 
// blocking assignments
module syncbad(input      clk,
               input      d,
               output reg q);
  reg n1;
  always@(posedge clk)
    begin
      n1 = d;  // blocking
      q  = n1; // blocking
    end//阻塞式赋值
endmodule

module mux2
  #(parameter width = 8)  // name and default value//令width为8,width当做8用
   (input  [width-1:0] d0, d1, 
    input      s,
    output [width-1:0] y);
  assign y = s ? d1 : d0; //赋值,s是1,y是d1,否则,y是d0
endmodule 

module sillyfunction(input  a, b, c, 
                     output y);//y是a,b,c的一个逻辑函数
  assign y = ~b & ~c | a & ~b;
endmodule

module testbench1();//测试模块
  reg  a, b, c;
  wire y;
  // instantiate device under test
  sillyfunction dut(a, b, c, y); //被测试的模块
  // apply inputs one at a time
  initial begin //模拟的数据
    a = 0; b = 0; c = 0; #10;//#num表示隔10ns
    c = 1; #10;
    b = 1; c = 0; #10;
    c = 1; #10;
    a = 1; b = 0; c = 0; #10;
    c = 1; #10;
    b = 1; c = 0; #10;
    c = 1; #10;
  end
endmodule

module testbench2();//模拟模块
  reg  a, b, c;
  wire y;
  sillyfunction dut(a, b, c, y);  // instantiate dut//被测试的模块
  initial begin // apply inputs, check results one at a time
    a = 0; b = 0; c = 0; #10;//模拟的数据
    if (y !== 1) $display("000 failed.");//y!==1,输出错误信息
    c = 1; #10;
    if (y !== 0) $display("001 failed.");
    b = 1; c = 0; #10;
    if (y !== 0) $display("010 failed.");
    c = 1; #10;
    if (y !== 0) $display("011 failed.");
    a = 1; b = 0; c = 0; #10;
    if (y !== 1) $display("100 failed.");
    c = 1; #10;
    if (y !== 1) $display("101 failed.");
    b = 1; c = 0; #10;
    if (y !== 0) $display("110 failed.");
    c = 1; #10;
    if (y !== 0) $display("111 failed.");
  end
endmodule 

000_1//测试文件,输入000结果应为1
001_0
010_0
011_0
100_1
101_1
110_0
111_0

module testbench3();//模拟模块
  reg  clk, reset;
  reg  a, b, c, yexpected;
  wire y;
  reg [31:0] vectornum, errors;    // bookkeeping variables
  reg [3:0]  testvectors[10000:0]; // array of testvectors//测试的数组
  
  // instantiate device under test
  sillyfunction dut(a, b, c, y); //被测试的模块
  
  // generate clock
  always     // no sensitivity list, so it always executes
    begin
      clk = 1; #5; clk = 0; #5;
    end
 
initial
    begin
      $readmemb(example.tv, testvectors);//读取测试文件
      vectornum = 0; errors = 0;//初始化,错误为0
      reset = 1; #27; reset = 0;//复位
    end

  always @(posedge clk)//时钟上升边缘,测试
    begin
      #1; {a, b, c, yexpected} = testvectors[vectornum];
    end

   always @(negedge clk)
    if (~reset) begin // skip during reset
      if (y !== yexpected) begin  //和预期不同,执行下列操作
        $display("Error: inputs = %b", {a, b, c});
        $display("  outputs = %b (%b expected)",y,yexpected);
        errors = errors + 1;//有错误输出信息,错误数加1
      end

      vectornum = vectornum + 1;
      if (testvectors[vectornum] === 4'bx) begin 
          $display("%d tests completed with %d errors", 
                vectornum, errors);//输出错误个数
        $finish;
      end
    end
endmodule

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