# Demo entry 6652646

11

Submitted by anonymous on Oct 24, 2017 at 16:23
Language: verilog. Code size: 7.9 kB.

```module example(input  a, b, c,
output y);
assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b &  c;
endmodule

module and3(input  a, b, c,
output y);
assign y = a & b & c;
endmodule
module inv(input  a,
output y);
assign y = ~a;
endmodule
module nand3(input  a, b, c ,output y);
logic n1;                   // internal signal
and3 andgate(a, b, c, n1);  // instance of and3
inv  inverter(n1, y);       // instance of inv
endmodule
module gates(input  [3:0] a, b,
output [3:0] y1, y2, y3, y4, y5);
/* Five different two-input logic
gates acting on 4 bit busses */
assign y1 = a & b;    // AND
assign y2 = a | b;    // OR
assign y3 = a ^ b;    // XOR
assign y4 = ~(a & b); // NAND
assign y5 = ~(a | b); // NOR
endmodule
module and8(input [7:0] a,
output y);
assign y = &a;
// &a is much easier to write than
// assign y = a[7] & a[6] & a[5] & a[4] &
//            a[3] & a[2] & a[1] & a[0];
endmodule
module mux2(input [3:0] d0, d1,
input  s,
output [3:0] y);
assign y = s ? d1 : d0;
endmodule
output s, cout);
logic p, g;   // internal nodes
assign p = a ^ b;
assign g = a & b;

assign s = p ^ cin;
assign cout = g | (p & cin);
endmodule

module mux2_8(input [7:0] d0, d1,
input  s,
output [7:0] y);
mux2 lsbmux(d0[3:0], d1[3:0], s, y[3:0]);
mux2 msbmux(d0[7:4], d1[7:4], s, y[7:4]);
endmodule

module tristate(input [3:0] a,
input  en,
output [3:0] y);
assign y = en ? a : 4'bz;
endmodule

module flop(input        clk,
input  [3:0] d,
output [3:0] q);
always@(posedge clk)
q <= d;                // pronounced “q gets d”
endmodule

module flopr(input  clk,
input  reset,
input [3:0] d,
output [3:0] q);

// synchronous reset
always@(posedge clk)
if (reset) q <= 4'b0;
else       q <= d;
endmodule
module flopr(input  clk,
input  reset,
input [3:0] d,
output [3:0] q);

// asynchronous reset
always @(posedge clk, posedge reset)
if (reset) q <= 4'b0;
else       q <= d;
endmodule
module flopren(input  clk,
input  reset,
input  en,
input [3:0] d,
output [3:0] q);
// asynchronous reset and enable
always@(posedge clk, posedge reset)
if      (reset) q <= 4'b0;
else if (en)    q <= d;
endmodule
module latch(input            clk,
input      [3:0] d,
output reg [3:0] q);
always@(*)
if (clk) q <= d;
endmodule

// combinational logic using an always statement
module gates(input      [3:0] a, b,
output reg [3:0] y1, y2, y3, y4, y5);
always@(*)       // need begin/end because there is
begin            // more than one statement in always
y1 = a & b;    // AND
y2 = a | b;    // OR
y3 = a ^ b;    // XOR
y4 = ~(a & b); // NAND
y5 = ~(a | b); // NOR
end
endmodule
module sevenseg(input      [3:0] data,
output reg [6:0] segments);
always@(*)
case (data)
//                     abc_defg
0: segments =       7'b111_1110;
1: segments =       7'b011_0000;
2: segments =       7'b110_1101;
3: segments =       7'b111_1001;
4: segments =       7'b011_0011;
5: segments =       7'b101_1011;
6: segments =       7'b101_1111;
7: segments =       7'b111_0000;
8: segments =       7'b111_1111;
9: segments =       7'b111_0011;
default: segments = 7'b000_0000; // required
endcase
endmodule
module priority_casez(input      [3:0] a,
output reg [3:0] y);
always@(*)
casez(a)
4'b1???: y = 4'b1000;  // ? = don’t care
4'b01??: y = 4'b0100;
4'b001?: y = 4'b0010;
4'b0001: y = 4'b0001;
default: y = 4'b0000;
endcase
endmodule

// Good synchronizer using
// nonblocking assignments
module syncgood(input      clk,
input      d,
output reg q);
reg n1;
always@(posedge clk)
begin
n1 <= d;  // nonblocking
q  <= n1; // nonblocking
end
endmodule

// blocking assignments
input      d,
output reg q);
reg n1;
always@(posedge clk)
begin
n1 = d;  // blocking
q  = n1; // blocking
end
endmodule

module mux2
#(parameter width = 8)  // name and default value
(input  [width-1:0] d0, d1,
input              s,
output [width-1:0] y);
assign y = s ? d1 : d0;
endmodule

module sillyfunction(input  a, b, c,
output y);
assign y = ~b & ~c | a & ~b;
endmodule

module testbench1();
reg  a, b, c;
wire y;
// instantiate device under test
sillyfunction dut(a, b, c, y);
// apply inputs one at a time
initial begin
a = 0; b = 0; c = 0; #10;
c = 1; #10;
b = 1; c = 0; #10;
c = 1; #10;
a = 1; b = 0; c = 0; #10;
c = 1; #10;
b = 1; c = 0; #10;
c = 1; #10;
end
endmodule
module testbench2();
reg  a, b, c;
wire y;
sillyfunction dut(a, b, c, y);  // instantiate dut
initial begin // apply inputs, check results one at a time
a = 0; b = 0; c = 0; #10;
if (y !== 1) \$display("000 failed.");
c = 1; #10;
if (y !== 0) \$display("001 failed.");
b = 1; c = 0; #10;
if (y !== 0) \$display("010 failed.");
c = 1; #10;
if (y !== 0) \$display("011 failed.");
a = 1; b = 0; c = 0; #10;
if (y !== 1) \$display("100 failed.");
c = 1; #10;
if (y !== 1) \$display("101 failed.");
b = 1; c = 0; #10;
if (y !== 0) \$display("110 failed.");
c = 1; #10;
if (y !== 0) \$display("111 failed.");
end
endmodule

1. Generate Clock

module testbench3();
reg  clk, reset;
reg  a, b, c, yexpected;
wire y;
reg [31:0] vectornum, errors;    // bookkeeping variables
reg [3:0]  testvectors[10000:0]; // array of testvectors

// instantiate device under test
sillyfunction dut(a, b, c, y);

// generate clock
always     // no sensitivity list, so it always executes
begin
clk = 1; #5; clk = 0; #5;
end

// at start of test, load vectors and pulse reset

initial
begin
vectornum = 0; errors = 0;
reset = 1; #27; reset = 0;
end

// apply test vectors on rising edge of clk
always @(posedge clk)
begin
#1; {a, b, c, yexpected} = testvectors[vectornum];
end
4. Compare with Expected Outputs
// check results on falling edge of clk
always @(negedge clk)
if (~reset) begin // skip during reset
if (y !== yexpected) begin
\$display("Error: inputs = %b", {a, b, c});
\$display("  outputs = %b (%b expected)",y,yexpected);
errors = errors + 1;
end
// Note: to print in hexadecimal, use %h. For example,
//       \$display(“Error: inputs = %h”, {a, b, c});

// increment array index and read next testvector
vectornum = vectornum + 1;
if (testvectors[vectornum] === 4'bx) begin
\$display("%d tests completed with %d errors",
vectornum, errors);
\$finish;
end
end
endmodule
// === and !== can compare values that are 1, 0, x, or z.
```

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