Demo entry 6656034

verilog flip flop

   

Submitted by anonymous on Oct 29, 2017 at 00:13
Language: verilog. Code size: 975 Bytes.

module flip_flops (clk, d, clk_enable, 
                   set, clear,
                   q1, q2, q3, q4);
input clk, d, clk_enable, set, clear;
output q1, q2, q3, q4;
reg q1, q2, q3, q4;


// d flip flop
always @ (posedge clk) q1 <= d;

// d flip flop with clk enable
always @ (posedge clk) 
    if (clk_enable == 1'b1) q2 <= d;
    else q2 <= q2;
    
/* d flip flop with clk enable, and with
   synchronous set and clear with set
   over riding clear */
always @ (posedge clk)
    if ( set == 1'b1) q3 <= 1'b1;
    else if ( clear == 1'b1) q3 <= 1'b0; 
    else if (clk_enable == 1'b1) q3 <= d;
    else q3 <= q3;
    
/* d flip flop with clk enable, and with
   assynchronous set and clear with set
   over riding clear */
always @ (posedge clk or posedge set or
          posedge clear)
    if ( set == 1'b1) q4 <= 1'b1;
    else if ( clear == 1'b1) q4 <= 1'b0; 
    else if (clk_enable == 1'b1) q4 <= d;
    else q4 <= q4;

endmodule 

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