Demo entry 6656982

1

   

Submitted by anonymous on Nov 02, 2017 at 11:24
Language: verilog. Code size: 373 Bytes.

module bitstream(clk,rst,newbit,finished,start,clk_2Hz,a,b,c,d,e,f,g);
	input clk;
	input rst;
	input newbit;
	inout clk_2Hz;
	inout finished;
	output start;
	output a;
	output b;
	output c;
	output d;
	output e;
	output f;
	output g;

   detect Module1(clk_2Hz,rst,newbit,finished,start,a,b,c,d,e,f,g);
	clock_divider Module2(clk,rst,clk_2Hz);

endmodule

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