Demo entry 6656984

11

   

Submitted by anonymous on Nov 02, 2017 at 11:27
Language: verilog. Code size: 4.1 kB.

module bitstream(clk,rst,newbit,finished,start,clk_2Hz,a,b,c,d,e,f,g);
	input clk;
	input rst;
	input newbit;
	inout clk_2Hz;
	inout finished;
	output start;
	output a;
	output b;
	output c;
	output d;
	output e;
	output f;
	output g;

   detect Module1(clk_2Hz,rst,newbit,finished,start,a,b,c,d,e,f,g);
	clock_divider Module2(clk,rst,clk_2Hz);

endmodule

module clock_divider(clk,rst,clk_2Hz);
	input clk;
	input rst;
	output clk_2Hz;
	reg [23:0]cnt;
	
	always@(posedge clk or posedge rst) begin //该时钟为内部时钟
		if(rst ==1'b1) begin//复位信号,计数器置零
			cnt<=24'd0;
		end	
		else begin
			if(cnt==24'd7999999)  //计数到399_9999时,计数器置零
				 cnt<=24'd0;
			else
			    cnt<=cnt+1'b1;  //一个时钟上升延,计数器加一
		end
	end
	
	assign clk_2Hz=(cnt<=24'd3999999)?1'b1:1'b0;  //当计数到199_9999时,clk_2Hz变为0
endmodule

module detect(clk_2Hz,rst,newbit,finished,start,a,b,c,d,e,f,g);

	input clk_2Hz;
	input rst;
	input newbit;
	output reg finished;
	output reg start;
	output reg a;
	output reg b;
	output reg c;
	output reg d;
	output reg e;
	output reg f;
	output reg g;
	
	parameter state0=4'b0000,
				 state1=4'b0001,
				 state2=4'b0010,
				 state3=4'b0011,
				 state4=4'b0100,
				 state5=4'b0101,
				 state6=4'b0110,
				 state7=4'b0111,
				 state8=4'b1000,
				 state9=4'b1001;

	reg [3:0] current_state;
	reg [3:0] next_state;
	reg [15:0] data;
	reg [3:0] count;
	
			 
	always@(posedge clk_2Hz or posedge rst) //2Hz时钟下
	begin
		if(rst==1'b1)begin  //复位信号时,所有参数置零
			current_state=state0;
			next_state<=state0;
			start<=1'b0;
			finished<=1'b0;
			data=16'd0;
			count<=4'd0;
			a=1'b0;
			b=1'b0;
			c=1'b0;
			d=1'b0;
			e=1'b0;
			f=1'b0;
			g=1'b0;
		end
		else 
		   begin
			current_state=next_state;
			
			if(finished==1'b1) begin//终止信号时,状态归零
				current_state=state0;
				finished<=1'b0;
			end
			
			else begin
					if(start==1'b1) begin //开始信号时
						data=data<<1;
						data[0]=newbit;
						if(count==4'd15) begin //计数到15时,即第十六比特进入数
							count<=4'd0;
							start<=1'b0;
			            a=1'b0;
			            b=1'b0;
			            c=1'b0;
			            d=1'b0;
			            e=1'b0;
			            f=1'b0;
			            g=1'b0;
							finished<=1'b1;
						end
						
						else begin
							count<=count+1'b1;  //未达到条件,继续计数
						end
					end
					
			 end
				
			case(current_state)
				state0:begin 
						 if(newbit==1'b0)begin
							 next_state<=state1;
							 a=1'b0;
							 b=1'b0;
							 c=1'b0;
							 d=1'b0;
							 e=1'b0;
							 f=1'b0;
							 g=1'b0;
						end
						 else
							 next_state<=state0;
				end
				
				state1:begin
						 if(newbit==1'b1) begin
							 next_state<=state2;
							 a=1'b1;
						 end
						 else
							 next_state<=state1;
				end
				
				state2:begin
						 if(newbit==1'b1) begin
							 next_state<=state3;
							 b=1'b1;
						 end
						 else
							 next_state<=state0;
				end
				
				state3:begin
						 if(newbit==1'b1) begin
							 next_state<=state4;
							 c=1'b1;
						 end
						 else
							 next_state<=state0;
				end
				
				state4:begin
						 if(newbit==1'b1) begin
							 next_state<=state5;
							 d=1'b1;
						 end
						 else
							 next_state<=state0;
				end
				
				state5:begin
						 if(newbit==1'b1) begin
							 next_state<=state6;
							 e=1'b1;
						 end
						 else
							 next_state<=state0;
				end
				
				state6:begin
						 if(newbit==1'b1) begin
							 next_state<=state7;
							 f=1'b1;
						 end
						 else
							 next_state<=state0;
				end
				
				state7:begin
						 if(newbit==1'b0) begin
							 next_state<=state8;
							 g=1'b1;
						 end
						 else
							 next_state<=state0;
				end
				
				state8:begin
						 start<=1'b1;  //到状态九时,开始信号激活
						 next_state<=state9;
				end
				
				state9:begin
						 
				end
				
				default:begin
						  next_state<=state0;
				end
				
			endcase
			
		end			
	end	
			
endmodule 

This snippet took 0.01 seconds to highlight.

Back to the Entry List or Home.

Delete this entry (admin only).