Demo entry 6682203

Verilog

   

Submitted by anonymous on Dec 07, 2017 at 13:51
Language: verilog. Code size: 304 Bytes.

1	module counter_1s(
2		clk, 
3		clk_1s
4		);
5		input wire clk;
6		output reg clk_1s;
7		reg [31:0] cnt;
8		always @ (posedge clk) begin
9			if (cnt < 50_000_000) begin
10				cnt <= cnt + 1;
11			end 
12			else begin
13				cnt <= 0;
14				clk_1s <= ~clk_1s;
15			end
16		end
17	endmodule

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