Demo entry 6684306

timer

   

Submitted by anonymous on Dec 15, 2017 at 05:56
Language: verilog. Code size: 380 Bytes.

wire tcarry1,tcarry2,tcarry3;
reg E;
ten_counter C1(enable,INIT[3:0],setvalue,CLK,count_result[3:0],tcarry1);
sixty_counter C2(tcarry1,INIT[11:4],setvalue,CLK,count_result[7:4],count_result[11:8],tcarry2);
ten_counter C3(E,INIT[15:12],setvalue,CLK,count_result[15:12],tcarry3);
always @(tcarry1,tcarry2)
begin 
	if (tcarry1&&tcarry2)
		E=1;
	else 
		E=0;
end
endmodule

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