Demo entry 6685312

Hao Meng

   

Submitted by anonymous on Dec 19, 2017 at 10:05
Language: vhdl. Code size: 11.6 kB.

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--															                  --
--	Author: Hao Meng										                  --
--	Student ID: 1729959										                  --
--	Module: EE3A1 Computer Hardware and Digital Design		                  --
--	Date: 19/12/2017										                  --
--	Description: This program is to process a series of calculations by using --
--  a register and an Arithmetic Logical Unit, a decoder and some D-type flip --
--  flops are also needed                                                     --  
--															                  --
--------------------------------------------------------------------------------

--                                     Decoder							      --
-- This part of code is going to split the input 32-bit number into three     --
-- address and opcode													      --
LIBRARY ieee;
USE ieee.std_logic_1164.all; 
USE ieee.std_logic_signed.all; 

ENTITY decoder IS
	PORT(in32bit:                      IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
	     clk:                          IN  STD_LOGIC;
	     address1, address2, address3: OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
		 opcode:                       OUT STD_LOGIC_VECTOR(5 DOWNTO 0));
END ENTITY decoder;

ARCHITECTURE simple OF decoder IS
BEGIN
	PROCESS(clk)
	BEGIN
		IF (rising_edge(clk)) THEN
			opcode   <= in32bit(31 downto 26);
			address1 <= in32bit(25 downto 21);
			address2 <= in32bit(20 downto 16);
			address3 <= in32bit(15 downto 11);
		END IF;
	END PROCESS	;
END ARCHITECTURE simple;





--                                   ALU							         --
-- This part of code is going to define the function of ALU, when the ALU    --
-- receive certain opcode, it will de the corresponding operation		     --
LIBRARY ieee;
USE ieee.std_logic_1164.all; 
USE ieee.std_logic_signed.all;

ENTITY alu is 
	port(a, b:  IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
	     opcode:IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
	     clk:   IN  STD_LOGIC;
	     c:     OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
END ENTITY alu;

ARCHITECTURE simple of alu is
BEGIN  
	PROCESS(clk)
	BEGIN
		IF(rising_edge(clk)) THEN 
			IF   (opcode= "001000")THEN c <= a + b;
			ELSIF(opcode= "001110")THEN c <= a - b;
			ELSIF(opcode= "001011")THEN c <= abs(a);
			ELSIF(opcode= "001010")THEN c <= -a;
			ELSIF(opcode= "000001")THEN c <= abs(b);
			ELSIF(opcode= "000110")THEN c <= -b;
			ELSIF(opcode= "000010")THEN c <= a or b;
			ELSIF(opcode= "000100")THEN c <= not a;
			ELSIF(opcode= "001100")THEN c <= not b;
			ELSIF(opcode= "000101")THEN c <= a and b;
			ELSIF(opcode= "000111")THEN c <= a xor b;
			END IF;
		END IF;
	END PROCESS;	
END ARCHITECTURE simple	;

	





--                                   Register							     --
-- This part of code is going to define a register, including the data 	     --
-- store in	each room, and the principle for wirting and reading	         --
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;   

ENTITY reg IS
PORT (address1, address2, address3: IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
      input:                        IN  STD_LOGIC_VECTOR(31 DOWNTO 0);	 
      clk:                          IN  STD_LOGIC;
      output1, output2:             OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
END ENTITY reg;

ARCHITECTURE simple OF reg IS
TYPE rom_array IS ARRAY ( 0 TO 31 ) OF STD_LOGIC_VECTOR ( 31 DOWNTO 0 );
SIGNAL rom_data: rom_array := (
X"00000000", X"00000000", X"00000000", X"00012CB6", X"000119FB", X"0000C233",
X"0000E632", X"0000D5E2", X"0000B493", X"000011F0", X"0000D68E", X"00001E53",
X"000140A6", X"0000C5DC", X"000157F1", X"0000BC27", X"0001451B", X"000108E7",
X"0000582C", X"000137E2", X"00006B12", X"000030BE", X"00006507", X"00011215",
X"00014C93", X"00005F21", X"00014062", X"000170C2", X"0000FE13", X"00010E32", 
X"00004F4C", X"00008FAD");

-- The following code is to define the writing and reading principle for 	 --
-- register. first, all the operation happen at the rising edge of a clock,  --
-- and if it detects the address3 is 0, which means the programme try to 	 --
-- write data into the location 0, and normally we would like to ignore this --
-- writing siganl from the input. Then,we would like to write the output1 and-- 
-- output2 the data it asked for by reading the data from the locations of 	 --
-- address1 and 2. What's more,we add a data forwarding logic, which when 	 --
-- address1 = address3, the data from input will directly write to output1.  --                                                                         
BEGIN	 
	PROCESS(clk)
	BEGIN  
		IF (rising_edge(clk)) THEN
		  IF(CONV_INTEGER (address3)=0) THEN
			output1 <= rom_data ( CONV_INTEGER (address1) );  
			output2 <= rom_data ( CONV_INTEGER (address2) );
		  ELSIF(address1=address3)THEN
		    output1 <= input;  
			output2 <= rom_data ( CONV_INTEGER (address2) ); 
			rom_data ( CONV_INTEGER (address3) ) <= input ;
		  ELSE
			output1 <= rom_data ( CONV_INTEGER (address1) );  
			output2 <= rom_data ( CONV_INTEGER (address2) ); 
			rom_data ( CONV_INTEGER (address3) ) <= input ;	   
		  END IF ;   
		END IF;
	END PROCESS;
END ARCHITECTURE simple;	


--                            D-type flip flop		   		                 --
-- This part of code define a simple D-type flip flop which could provide one--
-- clock pulse delay 												         --									 
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY dff IS
	port(D:  IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
	     clk:IN  STD_LOGIC;
	     Q:  OUT STD_LOGIC_VECTOR(5 DOWNTO 0));
END ENTITY dff;

ARCHITECTURE simple OF dff IS	  
BEGIN
	PROCESS(clk)
	BEGIN
		IF(rising_edge(clk)) THEN
			Q<=D;
		END IF;
	END PROCESS; 
END ARCHITECTURE simple;

--                            D-type flip flop2		   		                 --
-- This part of code define another simple D-type flip flop which could      --
-- provide one clock pulse delay 									         --
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY dff2 IS
	port(D:  IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
	     clk:IN  STD_LOGIC;
	     Q:  OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
END ENTITY dff2;

ARCHITECTURE simple OF dff2 IS	  
BEGIN
	PROCESS(clk)
	BEGIN
		IF(rising_edge(clk)) THEN
			Q<=D;
		END IF;
	END PROCESS; 
END ARCHITECTURE simple;


--                       D-type flip flop with reset		   		         --
-- This part of code define a D-type flip flop with reset button, which means--
-- when the flip flop detect a reset signal, it will not let any data passing--  
-- through                                                                   --
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY dffreset IS
	port(D:     IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
	     clk:   IN  STD_LOGIC;
	     Q:     OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
		 reset: IN  STD_LOGIC);
END ENTITY dffreset;

ARCHITECTURE simple OF dffreset IS	  
BEGIN
	PROCESS(clk)
	BEGIN
		IF(rising_edge(clk)) THEN
			IF(reset='1') THEN
				Q<="00000";
			ELSE
				Q<=D;
			END IF;
		END IF;
	END PROCESS; 
END ARCHITECTURE simple;


--                          Micro processor  	    	   		             --
-- This part of code define a microprocessor which combines all the parts    --
-- and functions of the components we defined before, and we also define the --
-- clock and reset in this part,we will talk about it later                  --
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY micro IS
END ENTITY micro;

ARCHITECTURE simple OF micro IS
SIGNAL linkbit1, linkbit2, linkbit3, in32bit:                         
                                              STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL input_address1, input_address2, linkbit5, linkbit56, linkbit6: 
                                              STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL linkbit41, linkbit42:                                          
                                              STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL clk, reset:                                                    
                                              STD_LOGIC;
BEGIN
g1: ENTITY work.reg(simple)
PORT MAP (address1=>input_address1, output1=>linkbit1, address2=>input_address2,
          output2=>linkbit2, address3=>linkbit6, input=>linkbit3, clk=>clk);	 
g2: ENTITY work.alu(simple)
PORT MAP (a=>linkbit1, b=>linkbit2, c=>linkbit3, clk=>clk, opcode=>linkbit42); 
g3: ENTITY work.decoder(simple)
PORT MAP (in32bit=>in32bit, clk=>clk, opcode=>linkbit41, address1=>input_address1,
          address2=>input_address2, address3=>linkbit5);
g4: ENTITY work.dff(simple)
PORT MAP (D=>linkbit41, Q=>linkbit42, clk=>clk);
g5: ENTITY work.dffreset(simple)
PORT MAP (D=>linkbit5, Q=>linkbit56, reset=>reset, clk=>clk);	
g6: ENTITY work.dff2(simple)
PORT MAP (D=>linkbit56, Q=>linkbit6, clk=>clk);

-- The following code is to define a clock which have a 20ns period          --
PROCESS
BEGIN
clk<='1';
wait for 10NS;
clk<='0';
wait for 10NS;
-- The following code is for the D-type flip flop with a reset, and this is  --
-- to detect if opcode is valid, if the opcode is invalid, then give the 	 --
-- reset signal to dffreset                                                  --
IF (linkbit41="001000")or(linkbit41="001110")or(linkbit41="001011")
	or(linkbit41="001010")or(linkbit41="000001")or(linkbit41="000110")
	or(linkbit41="000010")or(linkbit41="00100")or(linkbit41="001100")
	or(linkbit41="000101")or(linkbit41="000111") THEN
	reset<='0';
ELSE
	reset<='1';
END IF;
	
END process;
-- The following code is to define the input data by writing a new 32-bit 	 --
-- code every clock pulse The order of the data has been orgnized so it won't--
-- waste extra time to wait for the new result been written into the register--
-- (because of the data forwarding). The whole process will take 640ns(32 	 --
-- clock pulse) to have the final result.								     --
in32bit <=  
b"00100000011001000000100000000000"after 20 ns,
b"00100000101001100001000000000000"after 40 ns,
b"00100000001001110000100000000000"after 60 ns,
b"00111000010010000001000000000000"after 80 ns,
b"00111000001010010000100000000000"after 100ns,
b"00111000010010100001000000000000"after 120ns,
b"00111000001010110000100000000000"after 140ns,
b"00111000010011000001000000000000"after 160ns,
b"00100000001011010000100000000000"after 180ns,
b"00100000010011100001000000000000"after 200ns,
b"00100000001011110000100000000000"after 220ns,
b"00100000010100000001000000000000"after 240ns,
b"00100000001100010000100000000000"after 260ns,
b"00111000010100100001000000000000"after 280ns,
b"00111000001100110000100000000000"after 300ns,
b"00111000010101000001000000000000"after 320ns,
b"00111000001101010000100000000000"after 340ns,
b"00111000010101100001000000000000"after 360ns,
b"00100000001101110000100000000000"after 380ns,
b"00100000010110000001000000000000"after 400ns,
b"00100000001110010000100000000000"after 420ns,
b"00100000010110100001000000000000"after 440ns,
b"00100000001110110000100000000000"after 460ns,
b"00111000010111000001000000000000"after 480ns,
b"00111000001111010000100000000000"after 500ns,
b"00111000010111100001000000000000"after 520ns,
b"00111000001111110000100000000000"after 540ns,
b"00000000000000000000000000000000"after 560ns,
b"00100000001000100000100000000000"after 580ns,
b"00000000001000000000000000000000"after 600ns;

END ARCHITECTURE simple;					

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