Demo entry 6687507

Verilog

   

Submitted by anonymous on Dec 28, 2017 at 17:11
Language: verilog. Code size: 488 Bytes.

module top(
	input wire clk,
	input wire [4:0] sw,
	input wire Buzzer,
	output wire [7:0] LED,
	output wire [3:0] AN,
	output wire [7:0] SEGMENT
    );
	wire [7:0] num;
	wire [7:0] led;
	wire clk_1s,s_in,state;
	assign Buzzer=1;
	assign LED=~led;
	CreateNumber m0(sw[1:0],num);
	counter_1s m1(clk,clk_1s);
	ShiftRegb8 m2(clk_1s,s_in,sw[2],num,led);
	DispNum m3(clk,num,4'b1100,0,0,AN,SEGMENT);
	Mux2to1 m4(0,1,sw[3],state); 
	Mux2to1 m5(state,led,sw[4],s_in);
endmodule

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