Demo entry 6687724

ALU

   

Submitted by anonymous on Dec 30, 2017 at 14:04
Language: verilog. Code size: 711 Bytes.

`timescale 1ns / 1ps

module ALU(I0,I1,ALUCon,ALUResult,Zero);
	input [31:0]I0;
	input [31:0]I1;
	input [3:0]ALUCon;
	output [31:0]ALUResult;
	output Zero;
	reg [31:0]ALUResult;
	reg Zero;
	
	always @(I0 or I1 or ALUCon) 
	begin
	 	case(ALUCon)
                 4'b0010:	ALUResult=I0+I1;	//add
		 4'b0110:	begin
                                ALUResult=I0-I1;	//sub
                                if(I0 == I1) Zero = 1;
		                   else      Zero = 0;
                                end
		 4'b0000:	ALUResult=I0&I1;	//and
		 4'b0001:	ALUResult=I0|I1;	//or
		 4'b1100:       ALUResult=~(I0|I1);     //nor
		 4'b0111:	ALUResult=I0<I1;	//slt
		endcase
		
		
	end
endmodule

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