Demo entry 6737181

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Submitted by anonymous on Apr 29, 2018 at 19:07
Language: verilog. Code size: 1.4 kB.

module jp(clk100khz, din, scan, dout);

input clk100khz;
input[3: 0] din;

output[5: 0] scan;
output[7: 0] dout;

reg[5: 0] scan = 1;
reg[7: 0] dout = 0;
reg[7: 0] led[6];
reg[13: 0] fdcount = 0;
reg clk3_3hz = 0;

integer i;

initial
	for(i = 0; i < 6; i = i + 1)
		led[i] = 0;  // Initialize led

always@(posedge clk100khz)
begin
	// Scan led and output the corresponding result
	case(scan)
	6'h1: dout <= led[0];
	6'h2: dout <= led[1];
	6'h4: dout <= led[3];
	6'h8: dout <= led[4];
	6'h10: dout <= led[5];
	default: dout <= 0;
	endcase
	scan <= {scan[4: 0], scan[5]};

	// Frequency division
	if(fdcount == 14'd15000)
	begin
		clk3_3hz = ~clk3_3hz;
		fdcount <= 0;
	end
	else
		fdcount <= fdcount + 1;
end

always@(posedge clk3_3hz)
begin
	if(din != 4'b1111 && led[5] == 0)
	begin
		// Shift the value in led
		for(i = 1; i < 6; i = i + 1)
			led[i] <= led[i-1];

		// Update the value in led[0]
		case(din)
		4'b1110: led[0] <= 8'b00000110;  // 1
		4'b1101: led[0] <= 8'b01011011;  // 2
		4'b1011: led[0] <= 8'b01001111;  // 3
		4'b0111: led[0] <= 8'b01100110;  // 4
		4'b1100: led[0] <= 8'b01101101;  // 5
		4'b1010: led[0] <= 8'b01111101;  // 6
		4'b0110: led[0] <= 8'b00000111;  // 7
		4'b1001: led[0] <= 8'b01111111;  // 8
		default: led[0] <= 8'b01101111;  // 9
		endcase
	end
end
endmodule  // jp

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