Demo entry 6749201

王型性

   

Submitted by anonymous on Jun 12, 2018 at 13:36
Language: verilog. Code size: 315 Bytes.

`timescale 1ns / 1ps
module Pc(
	input clk,
	input rst,
	input PCWre,
	input [31:0] preAddress,
	output reg[31:0] address
	);

	always @(posedge clk or negedge rst) begin
		if (rst == 0) begin
			address <= 0;			
		end
		else if (PCWre == 1) begin
			address <= preAddress;
		end
	end

endmodule

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