Demo entry 6749202

王型性

   

Submitted by anonymous on Jun 12, 2018 at 13:37
Language: verilog. Code size: 5.1 kB.

`timescale 1ns / 1ps

module Cu(
	input [5:0] op,
	input zero,
	input sign,
	output reg PCWre,
	output reg ALUSrcA,
	output reg ALUSrcB,
	output reg DBDataSrc,
	output reg RegWre,
	output reg InsMemRW,
	output reg RD,
	output reg WR,
	output reg RegDst,
	output reg ExtSel,
	output reg[1:0] PCSrc,
	output reg[2:0] ALUOp
	);
	initial begin
		RD = 1;
		WR = 1;
		RegWre = 0;
		InsMemRW = 1;
		PCWre = 1; 
	end
	
	always @(op or zero or sign) begin
		// Ò»°ãÊÇ´ËÖµ
//		PCWre = 1; 		// halt
//		ALUSrcA = 0;	// sll
//		ALUSrcB = 0;	// addi ori sw lw  
//		DBDataSrc = 0;	// lw
//		RegWre = 1;		// sw beq bne bgtz j halt
//		InsMemRW = 1;
//		RD = 1;			// lw
//		WR = 1;			// sw
//		RegDst = 1;		// addi ori lw 
//		ExtSel = 1;		// ori

//		//PCSrc = 2'b00;
//		ALUOp = 3'b000;
	
		case(op)
			// add
		    6'b000000: begin
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 0;
				DBDataSrc = 0;
				RegWre = 1;
				InsMemRW = 1;
				RD = 1;
				WR = 1;
				RegDst = 1;
				ExtSel = 0;
				ALUOp = 3'b000;
				PCSrc = 2'b00;
		    end
		    // addi
			6'b000001: begin
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 1;
				DBDataSrc = 0;
				RegWre = 1;
				InsMemRW = 1;
				RD = 1;
				WR = 1;
				RegDst = 0;
				ExtSel = 1;
				ALUOp = 3'b000;
				PCSrc = 2'b00;
			end
			// sub
			6'b000010: begin
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 0;
				DBDataSrc = 0;
				RegWre = 1;
				InsMemRW = 1;
				RD = 1;
				WR = 1;
				RegDst = 1;
				ExtSel = 0;
				ALUOp = 3'b001;
				PCSrc = 2'b00;
			end
			// ori
			6'b010000: begin
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 1;
				DBDataSrc = 0;
				RegWre = 1;
				InsMemRW = 1;
				RD = 1;
				WR = 1;
				RegDst = 0;
				ExtSel = 0;
				ALUOp = 3'b011;
				PCSrc = 2'b00;
			end
			// and
			6'b010001: begin 
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 0;
				DBDataSrc = 0;
				RegWre = 1;
				InsMemRW = 1;
				RD = 1;
				WR = 1;
				RegDst = 1;
				ExtSel = 0;
				ALUOp = 3'b100;
				PCSrc = 2'b00;
			end
			// or
			6'b010010: begin 
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 0;
				DBDataSrc = 0;
				RegWre = 1;
				InsMemRW = 1;
				RD = 1;
				WR = 1;
				RegDst = 1;
				ExtSel = 0;
				ALUOp = 3'b011;
				PCSrc = 2'b00;
			end
			// sll
			6'b011000: begin 
				PCWre = 1;
				ALUSrcA = 1;
				ALUSrcB = 0;
				DBDataSrc = 0;
				RegWre = 1;
				InsMemRW = 1;
				RD = 1;
				WR = 1;
				RegDst = 1;
				ExtSel = 0;
				ALUOp = 3'b010;
				PCSrc = 2'b00;
			end
			// slt
			6'b011100: begin 
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 0;
				DBDataSrc = 0;
				RegWre = 1;
				InsMemRW = 1;
				RD = 1;
				WR = 1;
				RegDst = 1;
				ExtSel = 0;
				ALUOp = 3'b110;
				PCSrc = 2'b00;
			end
			// sw
			6'b100110: begin
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 1;
				DBDataSrc = 0;
				RegWre = 0;
				InsMemRW = 1;
				RD = 1;
				WR = 0;
				RegDst = 0;
				ExtSel = 1;
				ALUOp = 3'b000;
				PCSrc = 2'b00;
			end
			// lw
			6'b100111: begin 
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 1;
				DBDataSrc = 1;
				RegWre = 1;
				InsMemRW = 1;
				RD = 0;
				WR = 1;
				RegDst = 0;
				ExtSel = 1;
				ALUOp = 3'b000;
				PCSrc = 2'b00;
			end
			// beq
			6'b110000: begin 
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 0;
				DBDataSrc = 0;
				RegWre = 0;
				InsMemRW = 1;
				RD = 1;
				WR = 1;
				RegDst = 0;
				ExtSel = 1;
				ALUOp = 3'b001;
				if(zero == 0) begin
					PCSrc = 2'b00;
				end
				else if(zero == 1) begin
					PCSrc = 2'b01;
				end
			end
			// bne
			6'b110001: begin 
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 0;
				DBDataSrc = 0;
				RegWre = 0;
				InsMemRW = 1;
				RD = 1;
				WR = 1;
				RegDst = 0;
				ExtSel = 1;
				ALUOp = 3'b001;
				if(zero == 0) begin
					PCSrc = 2'b01;
				end
				else if(zero == 1) begin
					PCSrc = 2'b00;
				end
			end
			// bgtz
			6'b110010: begin 
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 0;
				DBDataSrc = 0;
				RegWre = 0;
				InsMemRW = 1;
				RD = 1;
				WR = 1;
				RegDst = 0;
				ExtSel = 1;
				ALUOp = 3'b101;
				if(zero == 1 || sign == 1) begin
					PCSrc = 2'b00;
				end
				else if(zero == 0 && sign == 0) begin
					PCSrc = 2'b01;
				end
			end
			// j
			6'b111000: begin
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 0;
				DBDataSrc = 0;
				RegWre = 0;
				InsMemRW = 1;
				RD = 1;
				WR = 1;
				RegDst = 0;
				ExtSel = 0;
				ALUOp = 3'b010;
				PCSrc = 2'b10;
			end
			// halt
			6'b111111: begin 
				PCWre = 0;
				ALUSrcA = 0;
				ALUSrcB = 0;
				DBDataSrc = 0;
				RegWre = 0;
				InsMemRW = 1;
				RD = 1;
				WR = 1;
				RegDst = 0;
				ExtSel = 0;
				ALUOp = 3'b000;
				PCSrc = 2'b00;
			end
			// slti
			6'b011011: begin
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 1;
				RegWre = 1;
				RegDst = 0;
				ExtSel = 0;
				ALUOp = 3'b110;
			end
		endcase
	end

endmodule

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