Demo entry 6776717

Cloudreve

   

Submitted by admin on Dec 04, 2018 at 10:14
Language: vhdl. Code size: 1.6 kB.

module aty(CLK,RSTn,Option_key,LED);
    input CLK,RSTn;
	output [4:0] Option_key;
	output [1:1] LED;

	reg [6:0] C1;
	reg [7:0] System_Seg,Option_Seg;
	reg [15:0] Counter;
	
	parameter SEGMENT = 7'd195;
	
	always@ (posedge CLK ,negedge RSTn)
	        if( !RSTn )
                begin
		            C1 <= 7'd0;
		      	    System_Seg <= 8'd0;
		      	    Option_Seg <= 8'd0;
                end
		    else if( C1 == SEGMENT )
		        begin
		            C1 <= 7'd0;
		      	    System_Seg <= System_Seg + 1'b1;
		        end
		      else if( System_Seg == 8'd255 )
		            System_Seg <= 8'd0;
		      else
			        C1 <= C1 + 1'b1;

    always@ (posedge CLK)
        if( Counter == 16'd50_000 )
            begin
                Counter <= 16'd0;
                case( Option_key )
					5'b1????:
                        if( Option_Seg < 8'd245 )
							Option_Seg <= Option_Seg + 8'd10;
				        else
							Option_Seg <= 8'd255;
					5'b?1???:
						if( Option_Seg > 8'd10 ) 
							Option_Seg <= Option_Seg - 8'd10;
				        else
							Option_Seg <= 8'd0;
					5'b??1??:
						if( Option_Seg < 8'd255 )
							Option_Seg <= Option_Seg + 8'd1;
				        else
							Option_Seg <= 8'd255;
					5'b???1?:
						if( Option_Seg > 8'd0 )
							Option_Seg <= Option_Seg - 8'd1;
			            else
							Option_Seg <= 8'd0;
					5'b????1:
						Option_Seg <= 8'd127;
				endcase	  
            end
        else
            Counter<= Counter + 16'd1;
	
    assign LED = ( System_Seg < Option_Seg ) ? 1'b1:1'b0;

endmodule

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