Demo entry 6787023

Raghunath

   

Submitted by anonymous on Apr 08, 2019 at 20:59
Language: vhdl. Code size: 1.8 kB.

-- Simple 4 Digit BCD Counter by raghu

library ieee;                    -- Standard ieee Library
use ieee.std_logic_1164.all;     -- Use std_logic_1164 package from ieee library
use work.CS254_EE214.all;

entity FOUR_DIGIT_BCD_COUNTER is -- Entity declaration
	port(CLK : in std_logic; -- Clock input of the counter
   	 
	     RSTN : in std_logic; -- Active low reset input of the counter
		  LDN : in std_logic; -- Active low load input of the counter
		  DIG : in std_logic_vector ( 1 downto 0); -- Select Pins of Latch Bank
		  D : in std_logic_vector(3 downto 0); -- Value to be assigned to the counter when LDN is active
		  O : out std_logic_vector(3 downto 0); -- Output of the counter
		  C : out std_logic); -- Carry Output Of The Counter
end FOUR_DIGIT_BCD_COUNTER;

architecture FUNCTIONALITY of FOUR_DIGIT_BCD_COUNTER is

signal Q1 , Q2 , Q3 , Q4 , D0 , D1 , D2 , D3 : std_logic_vector (3 downto 0);
signal S : std_logic_vector (1 downto 0);
signal C1 , C2 , C3,S0,S1,S2,S3,S4,S5,S6 : std_logic;

begin
		
		A0 : DIV_BY_FOUR port map (CLK , RSTN , S);
		
		M0 : strMUX_16X4 port map(Q2 , Q1 , Q4 , Q3 , S , O);
		
		L0 : LATCH_BANK3 port map (D , DIG , D0 , D1 , D2 , D3);--D0 lsb D3 msb of the counters 
		
		U0 : COUNTERSYNC port map (S(1) , '1' , RSTN , LDN , D0 ,'0' ,C1 , Q1);
		U1 : NOT_1 port map (C1,S0);
		U2 : COUNTERSYNC port map (S(1) , S0 , RSTN , LDN , D1 ,C1, C2 , Q2);
		U3 : NOT_1 port map (C2,S1);
		U9 : AND_1 port map (S1,S0,S5);
		U4 : OR_2 port map (C1,C2,S3);
		U5 : COUNTERSYNC port map (S(1), S5 , RSTN , LDN , D2 ,S3, C3 , Q3);
		U6 : NOT_1 port map (C3,S2);
		U10 : AND_1 port map (S2,S5,S6);
		U7 : OR_2 port map (S3,C3,S4);
		U8 : COUNTERSYNC port map (S(1) , S6 , RSTN , LDN , D3 , S4,C , Q4);--lsb Q1 msb = q4
		
		
		
end FUNCTIONALITY;

This snippet took 0.01 seconds to highlight.

Back to the Entry List or Home.

Delete this entry (admin only).